A fast – Locking Pulsewidth Controlled Clock Generator for High Speed SOC Applications
نویسندگان
چکیده
A fast-locking pulsewidth-controlled clock generator (PWCCG) based on delay locked loop is proposed in this paper. The coarse and fine delay lines and a time-to-digital detector permits the pulsewidth-controlled clock generator (PWCCG) to operate over a wide frequency range. A new dutycycle setting circuit is also presented in this paper that decides the preferred output duty cycle. Result of the proposed circuit achieves suitable for an input operating frequency range at 2 MHz, and an input duty cycle ranging from 30% to 70%, andproduce a programmable output duty cycle ranging from 30% to 66%.
منابع مشابه
Serbian Journal of Electrical Engineering
The clock distribution and generation circuitry forms a critical component of current synchronous digital systems. A digital system’s clocks must have not only low jitter, low skew, but also well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a mul...
متن کاملA fast-locking low-jitter pulsewidth control loop for high-speed pipelined ADC
A fast-locking, high-precision and low-jitter pulsewidth control loop for high-speed pipelined ADC is presented. Only through controlling the delay of rising edge to adjust duty cycle, the clock jitter could be suppressed greatly. An improved charge pump with a follower circuit and self-biased loop was designed to decrease the voltage ripples for higher accuracy and lower jitter. A start-up cir...
متن کاملLow Jitter ADPLL based Clock Generator for High Speed SoC Applications
An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. ...
متن کاملA Dual-Edge Triggered Phase Detector for Fast-Lock DLL
DLL is used as a clock generator due to its stable operation and relatively simple design. Analog DLL has the advantages of lower phase offset and lower clock jitter than digital DLL. However, locking speed is slow in analog DLL. This paper proposes a dual edge triggered phase detector to enhance the locking speed of analog DLL and suggests a closed-form expression of locking speed which can co...
متن کاملA Combined Vector and Direct Power Control for AC/DC/AC Converters in DFIG Based Wind Turbine
The doubly-fed generators (DFIG) have clear superiority for the applications of large capacity and limited-range speed control case due to the partially rated inverter, lower cost and high reliability. These characteristics enable the doubly-fed wound rotor induction machine to have vast applications in wind-driven generation.In this paper Combined Vector and direct power control (CVDPC) strate...
متن کامل